1. Field of the Invention
The present invention relates to a semiconductor integrated apparatus. More particularly, the present invention relates to a microcomputer system with multiple power supplies using at least two types of power supplies.
2. Description of the Related Art
Conventionally, a multiple power supply microcomputer system using many types of power supplies has been known. In particular, in a multiple power supply microcomputer system using two types of power supplies (for example, a high potential power supply VDDH and a low potential power supply (internal power supply) VDDL), a decline in low potential power supply VDDL output brings about various failure modes.
For example, a system which uses a low potential power supply VDDL for a central processing unit (CPU), a level shifter circuit, or the like, and uses a high potential power supply VDDH for the level shifter circuit, a peripheral PORT circuit, or the like will be considered. In a case of this system, in a fall-of-potential mode of a low potential power supply VDDL output (for example, refer to the T1b period in FIG. 5B), an output from an I/O (input/output) port output terminal P0 of the peripheral PORT circuit is made to be in an indefinite state. Further, in a case of this system, in a potential momentarily blackout mode (for example, refer to the T2b period in FIG. 5B), or a low potential power supply LOW (VSS) fixed (CPU coreless) mode (for example, refer to the T3b period in FIG. 5B) as well, an output from the I/O port output terminal P0 of the peripheral PORT circuit is made to be in the same way, i.e., in an indefinite state. As a result, due to excessive through currents (IVDDH) TA, TB, and TC which flow between the high potential power supply VDDH and a ground potential power supply VSS, problems such as device breaking, bonding wire cutting, and the like have been brought about.
To describe more concretely, for example, when a fall of potential in low potential power supply VDDL output reaches an inoperative area of a transistor (T1b), internal data of the CPU is made to be in an indefinite state. In accordance therewith, an output from the CPU as well is switched to be in an indefinite state. Then, an output from the level shifter circuit connected to the CPU is made to be in an indefinite state, and an output from the I/O port output terminal P0 to which an output from the level shifter circuit is supplied is made to be in an indefinite state. As a result, an excessive through current (IVDDH) TA flows between the high potential power supply VDDH and the ground potential power supply VSS, which brings about device breaking and bonding wire cutting.
On the other hand, for example, when a low potential power supply VDDL output is momentarily broken (T2b), an internal circuit output of the CPU is made to be in a floating state. In accordance therewith, an output from the CPU is switched to be in an indefinite state. Then, an output from the level shifter circuit is made to be in an indefinite state, and an output from the I/O port output terminal P0 is made to be in an indefinite state. As a result, an excessive through current (IVDDH) TB flows between the high potential power supply VDDH and the ground potential power supply VSS, which brings about device breaking and bonding wire cutting.
Further, in a test mode, for example, when a low potential power supply VDDL output is fixed to a LOW (VSS) level (T3b), an internal circuit output of the CPU is made to be in a VSS level fixed state. In accordance therewith, an output from the CPU is switched to be in a VSS level fixed state. Then, the level shifter circuit is made unable to normally operate, and an output from the level shifter circuit is made to be in an indefinite state, and an output from the I/O port output terminal is made to be in an indefinite state. As a result, an excessive through current (IVDDH) TC flows between the high potential power supply VDDH and the ground potential power supply VSS, which brings about device breaking and bonding wire cutting.
As described above, in a conventional multiple power supply microcomputer system, in a fall-of-potential mode, a potential momentarily blackout mode, or a low potential power supply LOW (VSS) fixed mode of a low potential power supply VDDL output, an output from the level shifter circuit is made to be in an indefinite state. Therefore, there have been problems that excessive through currents IVDDH flow between the high potential power supply VDDH and the ground potential power supply VSS, which brings about device breaking, bonding wire cutting, and the like.
Note that, as a prior art relating to the present invention, an apparatus in which unnecessary through current in an output circuit interface is suppressed has been already proposed (for example, refer to Jpn. Pat. Appln. KOKAI Publication No. 2003-288331). However, in this proposal, a power supply switch is provided in the level shift circuit used for the output circuit interface of the multiple power supply microcomputer, and that switch is controlled by control signals (a power-off control signal, a power-on control signal) at VDDH levels.